Automatic Test Pattern Generation (ATPG) is used to find a test pattern (an input or test sequence) that, when applied to an IC, allows a tester to determine between correct circuit behavior and faulty circuit behavior caused by defects. The generated test patterns can be used to test ICs after manufacture (i.e., manufacturing testing). The effectiveness of ATPG is often measured by the amount of modeled defects (i.e., fault models) that are detected and the number of generated patterns (i.e., pattern count).
Due to, for example, increased complexity and smaller feature sizes, testing chips (i.e., ICs) for manufacturing defects is becoming increasingly difficult. In addition to the increased transistor count, the use of new technology for the ICs can introduce new defect types which can lead to new types of defect tests. Along with the conventional stuck and transition fault models, accurate modeling and detection of timing related defects caused by process variation, power supply noise, crosstalk, design-for-manufacturing (DFM) related rule violations (such as single via nets) is critical to guarantee that manufactured silicon is defect free and does not posses a quality and reliability risk. As such, testing for fine delay defect or small delay defects (SDDs) is becoming a growing concern in the semiconductor industry. SDDs are defects that cause small delays relative to the timing margins allowed by the maximum operating frequency of an IC design.
Several EDA companies have launched commercial tools for supporting test pattern generation for screening SDD. To target SDDs, timing-aware ATPG tests have been developed. In timing-aware pattern generation, timing information is integrated, (e.g., from standard delay format (SDF) files) into the ATPG tool. The integrated timing information is used to guide the ATPG tool to detect faults through the longest paths of the IC in order to improve the ability to detect SDDs. Fault simulation uses the same timing information when grading the tests. Fault simulation, also referred to as fault grading, is performed to estimate fault coverage of the generated test patterns with respect to an IC. ATPG tools may measure and report the SDD coverage for a given set of test patterns according to metrics. Two such metrics are delay test coverage (DTC) and statistical delay quality level (SDQL).